1. Field
The present disclosure relates to an inverter device such that, even when there is a region in which flows current of a phase lagging with respect to the voltage of an alternating current output, it is possible to reduce output voltage waveform distortion.
2. Description of Related Art
Three-level inverter devices that generate alternating current voltage from three direct current potentials are being put to practical use in a wide field of industry. A schematic configuration of an inverter device that can output phase voltage at three levels of potential is shown in FIG. 11. This kind of inverter device is disclosed in JP-A-2007-028860. In FIG. 11, 1 is a direct current power supply, 2 is an inverter circuit, 3 is a filter circuit, and 4 is a load. The direct current power supply 1 is a power supply wherein a positive side power supply Psp and a negative side power supply Psn are connected in series. Output terminals of the direct current power supply 1 are a positive side terminal P of the positive side power supply Psp, a negative side terminal N of the negative side power supply Psn, and a neutral point terminal C, which is a connection point of the positive side power supply Psp and negative side power supply Psn. The positive side terminal P outputs a positive voltage V1 of the positive side power supply Psp. The negative side terminal N outputs a negative voltage −V2 of the negative side power supply Psn. The neutral point terminal C outputs a zero voltage Vz, which is an intermediate voltage of the direct current power supply 1.
The inverter circuit 2 is configured of switching elements Q1 and Q2 and switch elements S1 and S2. The switching elements Q1 and Q2 are connected in series, and connected to both ends of the direct current power supply 1. A connection point of the switching elements Q1 and Q2 is an output terminal U that outputs an alternating current voltage Vout. The switch elements S1 and S2 are connected in anti-parallel, configuring a bidirectional switch BS. The bidirectional switch BS is connected between the neutral point terminal C and the output terminal U. The filter circuit 3 is a circuit formed by a reactor Lf and capacitor Cf being connected in series. The filter circuit 3 is connected between the output terminal U and the neutral point terminal C. The load 4 is connected to both ends of the capacitor Cf. A sinusoidal load voltage Vload obtained by eliminating harmonic components from the output voltage Vout of the inverter circuit 2 is output to both ends of the capacitor Cf.
Firstly, a description will be given of an operation of the inverter circuit 2 when a load voltage Vload with positive polarity is output. FIG. 12 is a diagram showing the relationship between a control signal of each element and output voltage Vout. Each element is turned on when the control signal thereof is at a high level (hereafter referred to as H), and turned off when the control signal thereof is at a low level (hereafter referred to as L). FIG. 12 part (a) shows the temporal change of a first pulse width modulation signal (PWM signal 1). The PWM signal 1 is a signal that forms a reference for generating the control signals of the switching element Q1 and switch element S2. The PWM signal 1 repeatedly switches between H and L. The control signal of the switching element Q1 is H or L in synchronization with the PWM signal 1 (FIG. 12 part (c)). The control signal of the switch element S2 inverts the H and L of the PWM signal 1, and is a signal to which an idle period Td is added (FIG. 12 part (f)). The idle period Td is a period for turning the two elements off together in order to prevent a short-circuiting of the switching element Q1 and switch element S2.
FIG. 12 part (b) shows the temporal change of a second pulse width modulation signal (PWM signal 2). The PWM signal 2 is a signal that forms a reference for generating the control signals of the switching element Q2 and switch element S1. The PWM signal 2 is constantly L in this period. The control signal of the switching element Q2 is constantly L, in accordance with the PWM signal 2 (FIG. 12 part (d)). The control signal of the switch element S1 is constantly H, in accordance with a signal wherein H and L of the PWM signal 2 are inverted (FIG. 12 part (e)).
When each element carries out an on/off operation based on the heretofore described control signals, voltage Vout of a pulse train of positive polarity is output between the output terminal U and neutral point terminal C (hereafter referred to as between the terminals U and C). The voltage Vout is pulse width modulated, and the amplitude thereof is the voltage V1 of the direct current power supply Psp.
Next, a description will be given of an operation of the inverter circuit 2 when voltage Vout with negative polarity is output. FIG. 13 is a diagram showing the relationship between a control signal of each element and the output voltage Vout. FIG. 13 part (a) shows the temporal change of the PWM signal 1. The PWM signal 1 is constantly L in this period. The control signal of the switching element Q1 is constantly L, in accordance with the PWM signal 1 (FIG. 13 part (c)). The control signal of the switch element S2 is constantly H, in accordance with a signal wherein H and L of the PWM signal 1 are inverted (FIG. 13 part (f)).
FIG. 13 part (b) shows the PWM signal 2. The PWM signal 2 repeatedly switches between H and L. The control signal of the switching element Q2 is H or L in synchronization with the PWM signal 2 (FIG. 13 part (d)). The control signal of the switch element S1 inverts the H and L of the PWM signal 2, and is a signal to which an idle period Td is added (FIG. 13 part (e)). The idle period Td is a period for turning the two elements off together in order to prevent a short-circuiting of the switching element Q2 and switch element S1.
When each element carries out an on/off operation based on the heretofore described control signals, voltage Vout of a pulse train of negative polarity is output between the terminals U and C. The voltage Vout is pulse width modulated, and the amplitude thereof is the voltage V2 of the direct current power supply Psn.
As heretofore described, the output voltage Vout is a pulse width modulated pulse train voltage, and includes harmonic components. The harmonic components included in the output voltage Vout are eliminated in the filter circuit 3. In the same way, harmonic components included in an output current Tout of the inverter circuit 2 are eliminated in the filter circuit 3. As a result of this, the sinusoidal alternating current Vload is applied to the load 4. Also, a sinusoidal alternating current Iload flows into the load 4.